A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

A test pattern generator generates a pseudorandom that can be weighted to reduce the fault coverage in built-in self-test. The objective of this paper is propose new TPG for scan-based BIST architecture. motivation work generate efficient patterns enabling scan chains with reduced power consumption and area. Additionally, pseudo-primary seed maximized obtain considerable length patterns. maximum-length are executed by assigning separate weights specific using weight-enabled clock. This approach reduces hardware overhead achieves low 26.7 nW. Moreover, proposed applied two different test-per-scan architectures accurate results. also generated fewer switching transitions higher coverages 98.81% 97.35% architectures. process observed six other circuits under as their chains. simulation results tested SilTerra 0.13 ?m on Mentor Graphics IC design platform. Furthermore, enlarged bit TPG, which compared accomplish performance strategies. experimental tabulated existing potential designs.